Pulse duration measuring arrangement

ABSTRACT

To convert the duration of single sequentially occurring pulses to proportional continuous current characteristic, for example voltage or current, a capacitor is charged by a constant current during the duration of the pulse, and condenser charge measured; to permit use of components in the circuit at operating points of their operating characteristics which exhibit sharp bends, rather than gradual transition, the charging of the condenser is delayed by a predetermined time period with respect to the start of the pulse to be measured, and, the capacitor is maintained at a predetermined initial charge corresponding to the charge which would otherwise accumulate during the delay period. Two capacitors, in two alternately activated channels are used to permit partial discharging, and recharging to a reciprocative level of one capacitor, while the other holds its previous charge for continuous indication of pulse length of the previous pulse.

United States Patent 1 Wessel [4 1 May 1, 1973 [54] PULSE DURATIONMEASURING 3,582,678 6/1971 Davis etal ..324/l89 ARRANGEMENT PrimaryExaminer-Alfred E. Smith [75] Inventor. 3211f}, Wessel, Schwieberdingen,Gery y & Frishauf [73] Assignee: Robert Bosch GmbH, Gerlingen- [57]ABSTRACT Schluerhohe Germany To convert the duration of singlesequentially occur- [22] Filed: Oct. 4, 1971 ring pulses to proportionalcontinuous current characteristic, for example voltage or current, acapacitor is [21] Appl' 186030 charged by a constant current during theduration of the pulse, and condenser charge measured; to permit [30]Foreign Application Priority Data use of components in the circuit atoperating points of O 7 1970 G P 49 3 2 their operating characteristicswhich exhibit sharp rmany l bends, rather than gradual transition, thecharging of the condenser is delayed by a predetermined time [2%] periodwith respect to the start of the pulse to be t i1- "an 0 I Sured, and,the capacitor is maintained at a predeter- 1 le 0 care E, mined chargecorresponding to e charge 7 304/294 which would otherwise accumulateduring the delay period. Two capacitors, in two alternately activated[56] References Cited channels are used to permit partial discharging,and UNITED STATES PATENTS recharging to a reciprocative level of onecapacitor,

while the other holds its previous charge for continu- 3,585,502 6/1971Barkley ..324/189 115 indication of pulse length of the previous pulse.3,466,550 9/1969 Wolf et al.. ....324/78 E 3,626,204 12/1971 Brandon..324/78 E 15 Claims, 3 Drawing Figures f0 CONDE/MSEB D/SC/MRGE C/ACBIST/IBLE 10 j ,4 J z a; 1, R HE A l/ 7/ .sz/armcr/ofl 6 1 574 5 J5sraexms "M V M/ verze Egg gigs j, ZOZZENJER c/ 0/7 0 slvssieMO/VOJT/lfilf D/Fff/Pf/l/flflibk 5722 PATENTEB MAY 1 1975 SHEET 3 OF 3Awewrop A a/f' h zr as PULSE DURATION MEASURING ARRANGEMENT The presentinvention relates to a circuit arrangement to transform pulse durationof electrical pulses into a proportional electrical current, or voltage,and more particularly to this type of arrangement in which a condenseris charged by a constant current and the charge on the condenser, duringthe pulse duration, is measured.

Pulse duration measuring apparatus in which the pulse duration ismeasured by measuring a representative charge on the condenser areknown. Such measuring arrangements are used, among other applications,to adjust and supervise electronically controlled fuel injectionarrangements. Electronically controlled fuel injection arrangements, forexample are illustrated and described in US. Pat. No. 3,483,851. Fuel,under practically constant pressure is applied to electromagneticallycontrolled injection valves which are opened by means of electricalpulses, the pulse duration determining the amount of fuel beinginjected.

It is an object of the present invention to provide a pulse durationmeasuring apparatus which can be used under machine shop conditions,which is simple, rugged, and still accurate, and in which the durationof even single pulses can be measured.

The measuring apparatus of the present invention is based on the knownprinciple of the linear charge on a condenser during a pulse. Inaccordance with this known method, the voltage on the condenser, afterthe end of the pulse, is determined, this voltage being a representationof the pulse duration. It has been customary to charge the condenser,starting at a pulse time t 0, the initial voltage being 0. Such anarrangement requires a circuit in which the characteristics ofelectronic components exhibit a sharp break, or bend, at the voltagevalue 0. It is difficult to obtain an overall characteristic of thistype with customary circuit components.

SUBJECT MATTER OF THE PRESENT INVENTION Briefly, to provide a simplecircuit in which a linear relationship between pulse duration andproportional charging current, or final charge voltage is obtained, acertain delay period is inserted into the charge operation of thecondenser with respect to the start of the pulse. Thus, the charge onthe condenser, based on pulse duration, is started only after a certaintime delay with respect to the start of the pulse. The condenser is keptat a predetermined charge level until the charge placed thereon based onpulse duration is connected. The initial charge voltage isrepresentative of the delay time.

The arrangement avoids the necessity of utilizing components which havea sharp bend in their operating characteristics at the point of absolutezero to provide exact proportionality of current supply.

In accordance with a feature of the invention, successively occurringpulses, of a series or train of pulses are successively applied,alternatingly, to charge one or the other of a pair of condensers.Preferably, a bistable electronic switch, in the form ofa flip-flop isprovided, the flip-flop having a pair of output terminals which areoppositely polarized. The outputs are connected, each, over an AND-gatewith the charging arrangement of the respective condensers. AdditionalAND-gates are provided, connecting the condensers to appropriatedischarge and measuring devices or indicators. When the AND-gates areenabled, by means ofa control connection, the particular pulse underconsideration directs charge and discharge to the one or the othercondenser so that, while one condenser is being charged, the charge onthe other can. be measured and indicated.

It is preferable to utilize condensers which have relatively smallvalues of capacity. This requires a low loading on the condenser duringtesting for the charge thereon which, in turn, requires a high inputresistance measuring instrument. In accordance with a feature of theinvention, the measuring circuit includes a transistor connected as anemitter follower, particularly in Darlington circuit. One transistor,each, is connected to the respective condensors, which are alternatelycharged, the output of the transistors being measured in an indicatinginstrument.

The invention will be described by way of example with reference to theaccompanying drawings, wherein:

FIG. 1 is a schematic block circuit diagram of a circuit arrangement tomeasure the pulse duration, diagrams of signals being schematicallyindicated in, or next to, some of the circuit components;

FIG. 2 is a timing and pulse graph used in the explanation of theinvention; and

FIG. 3 is a circuit diagram of an operating embodiment.

Referring to FIG. 1: The circuit is particularly designed to measure thepulse duration of pulses which can succeed each other in irregularintervals, in time, and in which the pulse duration of succeeding pulsesmay vary. A current is to be provided which is proportionate to pulseduration. FIG. 1 illustrates the indicator as a milli-ampere meter 10although, of course, other indicators, recorders and the like may beused. The circuit arrangement includes a pair of charging condensers 11,12 which, during the duration of the pulse to be measured, are chargedby a constant current. As the condensers charge, the voltage due to thecharge being stored on the condenser rises, as schematically indicatedas U with subscripts 1 and 2 indicating the relationship with respect tothe condensers ll, 12, respectively. The charge U will be proportionateto pulse duration. At the end of the pulse, the charge, that is thevoltage thereacross, can be measured. To measure the charge on thecondenser, a transistor T,, T respectively, is provided. The transistorsare connected with their collectors to indicator 10 and are connected inemitter follower circuits to have high input impedance. The emitterresistances R R are adjustable. A particularly desirable arrangementutilizes field effect transistors for transistors T T or a pair of npntransistors in Darlington circuit, as seen in FIG. 3.

The current characteristics of electronic circuit elements, particularlysolid state elements of this type do not exhibit a sharp bend when theychange from blocked to conductive condition but rather exhibit a gradualtransition. In order to provide a sharp transfer of characteristics, thecircuit in accordance with the present invention is so arranged that thetransistors T and T are operated only within the linear region of theiroperating characteristics.

The circuit, in accordance with FIG. 1, includes a differentiator l5 anda monostable multivibrator 20, an impulse subtraction circuit 30, and asubsequent inverter stage 38. A bistable multivibrator 40 is provided,and so connected that subsequent consecutive pulses of a train of pulsesare alternately applied to a pair of outputs A A exhibiting oppositepolarity, to charge condensers 11, 12 alternately, and to also controlconnection of the particular read-out circuit which is appropriate tothe condenser which has been charged with a just preceding pulse.

The condensers are to be discharged, in accordance with the invention,in advance of the next subsequent charging cycle not completely, but toa predetermined fixed remanent voltage. Each one of the condensers has adischarge arrangement connected thereto. To permit multivibrator 40 tocontrol charge and discharge, each of the condensers is connected to apair of AND-gates 60, 80, and 70, 90, respectively. Output A ofmultivibrator 40 is connected to a first AND-gate 60 and over it withthe charging arrangement L of the first condenser 11, and further over athird AND-gate 80 with the discharge circuit D associated with thecondenser 11. The other output A of flip-flop 40 is connected over asecond AND-gate 70 with a charging arrangement L and over a fourthAND-gate 90 with a discharge circuit D of the second condenser 12.

Specifically, the circuit is constructed as shown in FIG. 3: A pulse tobe measured, or a series of pulses J are first applied to differentiator15 which includes a coupling condenser 16 of small capacity, a pair ofvoltage dividers 17, 18 and a diode 19. The diode is connected to the'base of input transistor 21 of a monostable multivibrator 20. Themonostable multivibrator provides a delay time t starting at the sametime as the start of the pulse J to be measured. The multivibratorincludes an output transistor 22 connected with its base over aresistance 23 to the collector of input transistor 21. Current issupplied from a main positive bus 25, and supplied over a resistance 24.The collector of output transistor 22 is connected to collectorresistance 26 (and then to positive bus and over a condenser 27 back tothe base of transistor 21. Condenser 27, together with input transistor21, when in quiescent state, provides current through base resistance 28and provides the timing circuit, which determines the duration t of thedelay time. As soon as one of the pulses J begins, the input transistor21 will block, output transistor 22 will become conductive and thecharge on the condenser 27 is applied back to the input transistor andholds the input transistor blocked for a duration t corresponding to adelay pulse 1,. The pulse duration t, of the pulse to be measured isthus shortened by the duration t The collector of input transistor 21 aswell as the input electrode of the coupling condenser 16 are connectedover a pair of diodes 31, 32 to the base of a transistor 34 forming partofa pulse subtraction stage. The base of transistor 34 is connected tothe common negative bus 35 over a base resistance 36. The collector isconnected over collector resistance 37 with positive bus 25. Transistor34 can be blocked only during that period of time when theinputelectrode of coupling condenser 16 is held negative due to a pulse.1 and when the collector of the input transistor is at, orapproximately at negative potential. This condition is illustrated inFIG. 2 by lines P (second line of the graph) in which the collectorpotential of transistor 21 is indicated. During the blocking oftransistor 21, the collector is at positive voltage. Transistor 34 ofthe subtraction stage 30 can block only when the monostablemultivibrator 20 returns to stable output state. In accordance with FIG.3, this occurs only at the time t;,, which is delayed with respect tothe beginning of the pulse t by the delay time t,,, as indicated withrespect to pulse J first line of the graph of FIG. 2. At point t theremainder of the pulse J will switch bistable multivibrator 40, actingas a transfer switch, in its opposite state from that .in which it hadpreviously been set.

Bistable flip-flop 40 has a first npn transistor 41, and a second npntransistor 51 which are always in opposite state of conduction, orblocking, respectively. The bases of the two transistors are connected,each, over a resistance 44, 54, respectively, with negative bus 35. Thecollector of the first transistor 41 is connected over a resistance 47with positive bus 25. This is the second output A of the bistablemultivibrator 40. The collector of the first transistor 41 isadditionally connected over a resistance58 and a diode 56 to the base ofthe second transistor 51. The collector of the second transistor 51forms the first output A of the alternate switch and is connected withpositive bus 25 over a resistance 27. Additionally, the collector isconnected over a resistance 48 and diode 46 to the base of the firsttransistor 41. The multivibrator is symmetrically built and is completedby a pair of coupling condensers 43, 43', of equal value, one electrodeof each being connected to the collector of transistor 34 of subtractionstage 30. The other electrode of condenser 43 is connected overresistance 42 to the collector of transistor 41 and to the cathode ofadiode 45, the anode of which is connected to the anode of diode 46 and,in turn, to the feedback resistance 48. Similarly, the second electrodeof coupling condenser 43' is connected to the collector of the secondtransistor 51 over a resistance 52, and to the base of transistor 51over a diode 55 which is coupled to the diode 56 and feedback resistance58.

To prevent spurious switch-over and to insure holding of a definedoutput state, the bases of the transistors 41, 51 are interconnected bya holding circuit formed of resistance 59 and condenser 53.

Referring again to FIG. 2, potential P (fourth line of graph) at theoutput of the inverter stage 38 (collector potential of the invertertransistor 38) is positive up to point t;,. Thus, transistor 61 (FIG. 3)of the first AND-gate is held conductive over diode 67. The chargingcurrent provided by charging transistor 111, the value of which is setby resistance 112, does not charge condenser 11 but rather is bypassed.At point charge is initiated by blocking of the AND-gate transistor 61,so that the charging current is applied over diode 113 to the electrodeof condenser 11 which is connected to an input or scanning transistor Tconnected as an emitter follower to transistor T The charging current isconstant and thus provides a voltage U rising linearly during theduration of the pulse J m which, when the pulse terminates at point treaches a value U (FIG. 2). The scanning or measuring circuit includingtransistors T and T is placed in circuit at the time to indicate thecharge value U At that point, the first transistor 41 of circuit 40 isconductive, as indicated by the graph representative of the secondoutput A showing that the voltage returns to zero.

The two transistors T and T connected as emitter followers in Darlingtoncircuit are connected to the indicating instrument It). The currentthrough the instrument is determined by the resistance R and through thefirst transistor 41, which is proportional to the voltage U, oncondenser 11. This current is practically constant during the measuringcurrent flow, since the indicating current hardly loads condenser 1].Scanning and indication continues until the termination of the nextpulse J (FIG. 2) at time t, (first and second lines, FIG. 2). At thattime the indicator will then measure the voltage on the second storagecondenser 12, as determined by the second half of the circuit. At thepoint time 2 the first output A of the switch-over circuit 40 willrevert to the potential of the negative bus 35. The AND-gate transistor81 of the third AND-gate 80 is blocked and the previously blockeddischarge transistor 101 will become conductive. Discharge of thecharging condenser 11 occurs rapidly over the diode 114, poled to beconductive in the discharge direction, and over the collector-emitterpath of the discharge transistor 101, until a voltage value U, isreached. This voltage U is determined by the ratio of the tworesistances 105, 107. The remaining voltage will be other than zero, andwill be retained on the storage condenser 11 until the beginning of thenext charging cycle. This remanent voltage is selected to have such avalue that it corresponds to the charge which would accumulate duringthe delay pulse J,,.

The storage condenser 11 should not be charged at all over theresistance 105 during the period of time I that is, while the dischargetransistor 101 is in blocking state. To prevent any possibility ofcharge being applied over resistance 105, the collector of transistor 81is interconnected by means of a diode 108 to resistance 105. Transistor101 and transistor 81 are always in opposite states of conduction, thatis, when one is blocked the other one is conductive. Diode 106 providesinterconnection to the collector of transistor 101. The junction ofdiode 106 and resistance 105 is held at negative potential by theconductive AND gate transistor 81 when the discharge transistor 101 isblocked.

The second storage condenser 12 is similarly connected, and the circuitis symmetrical with respect thereto. The second AND-gate 70 has atransistor 71 with a collector resistance 72, a base resistance 74, anda pair of input diodes 76, 77, connected over resistance 75 to the baseof transistor 71. Diode 76 is connected to the second output A of theswitch-over circuit 40; diode 77 is connected to the collector of theinverter transistor 38. Transistor 71 is brought into blocked state upto the end t of the delay pulse 1,, which is initiated simultaneouslywith the start of the next pulse J, to be measured. Blocking oftransistor 71 then permits the charging circuit L associated with thetransistor 121 to provide a charging current to condenser 12. Theremaining pulse J of the next pulse J causes the voltage on condenser 12to rise linearly until time that is, until the end of the pulse beingmeasured. The voltage on condenser 12 will rise to a value U Asindicated in the graph of FIG. 2, the pulse J is shorter than the pulse1, and thus the value of the voltage U is less than the voltage Umeasured during the pulse J The voltage U is sensed by the circuitincluding emitter follower transistors T and T and provides a currentindicated as J corresponding to the voltage U this current beingindicated in instrument 10 until, in the previously described manner, atthe end of the third pulse J at time t,,, the first condenser 11 isagain placed in circuit. As can be seen from FIG. 3, the collectors ofthe four transistors operative in the measuring circuit are connected toa common collector line 10', which is connected to the meter 10.

As is apparent from the last graph of FIG. 2, the measuring indicationis one step out of phase with the pulse actually being measured.

The measuring arrangement in accordance with the present invention hasthe particular advantage that each pulse can be measured with a highdegree of accuracy and a sufficiently long period of time is availablefor reading of any one of the pulses. This is particularly importantwhen electronically controlled fuel injection systems are to beadjusted, in which, due to operating conditions of the apparatus withwhich the systems are used, such as fixed values of pressure in theintake manifolds of the internal combustion engines, pulses ofpredetermined time duration must be obtained. An initial setting for thevarious pulses can be provided and adjustment of pulse duration, thatis, of the circuit causing the pulses to have predetermined durationscan readily be carried out since personnel adjusting the fuel injectionsystem need concern itself solely with reading of the indicatinginstrument. The start of the pulses can be adjusted, as desired, byoperating personnel, the pulse duration being measured on the instrumentconstantly and continuously until the next pulse comes along, theduration of which again will be indicated until the next succeedingpulse, and so on.

Various changes and modifications may be made within the inventiveconcept, particularly in the circuit, in the arrangement of the gatesand the like.

I claim:

1. Pulse length measuring circuit arrangement to provide an electricalvoltage or current representative of duration of input pulses comprisingat least one charging condenser;

a constant current source;

means connecting the constant current source to charge the condenserduring occurrence of the pulse; means sensing the charge on thecondenser to provide a measure of the duration of the input pulse;

means discharging the condenser to a predetermined charge levelrepresentative of a predetermined time duration to provide apredetermined minimum charge on the condenser;

and delay means connected to delay, by said predetermined time,connection of the constant current source to the condenser by saidconnection means, to avoid charging the condenser from completelydischarged state.

2. Circuit arrangement according to claim 1, to measure the timeduration of individual pulses of a train of pulses, wherein a pair ofcondensers are charged in alternate sequence.

3. Circuit arrangement according to claim 2, including a bistableflip-flop having a pair of oppositely poled outputs;

AND-gates connected to said condensers, and means connecting the outputsto respective AND-gates associated with the condensers to selectivelyenable said AND-gates and thus application of pulses to one or the othercondenser andto permit readout of the charge from one or the othercondenser.

4. Circuit arrangement according to claim 3, wherein said sensing meansincludes a pair of transistors one, each, being connected to arespective condenser, a measuring instrument, the output of therespective transistor being applied in parallel to the measuringinstrument, said transistors being connected to the outputs of thebistable flip-flop and selectively enabled.

5. Circuit arrangement according to claim 2, including a bistableflip-flop having a pair of oppositely poled outputs, and furthercomprising a pair of input AND- gates, one each gate being connected toa respective charging circuit of a condenser;

, a pair of output AND-gates, one each output AND- gate being connectedto a respective discharge circuit of the condenser;

and means interconnecting the outputs from the flipflop and the chargingcircuit of one condenser while connecting the discharge circuit of theother, in alternate sequences, to permit reading of the charge on onecondenser while the other is charging, and vice versa. 6. Circuitarrangement according to claim 1, wherein the sensing means comprises atransistor having its base connected to the condenser.

7. Circuit arrangement according to claim 6, wherein the transistor isconnected as an emitter-follower.

8. Circuit arrangement according to claim 7, wherein the transistor is afield effect transistor.

9. Circuit arrangement according to claim 6, wherein the transistor isconnected in a Darlington circuit.

10. Circuit arrangement according to claim 6, wherein the sensing meansincludes a current measuring instrument connected to the transistor.

11. Circuit arrangement according to claim 1, wherein the condenserdischarge means comprises a control transistor (101);

a source of voltage (25, 35); a voltage divider network (105, 107)serially connecting the emitter-collector path to the source;

and means (114) connecting the condenser (11) to the tap point of thevoltage divider in the emittercollector path of the control transistorto dischargethe condenser to a level determined by the voltage divisionratio of the voltage divider and the resistance of the emitter-collectorpath of the transistor.

12. Pulse length measuring apparatus comprising a single indicator meansa single pulse source (J);

a delay circuit (15, 20, 30) delaying start of the pulse by apredetermined time (t,,) but being ineffective to delay termination ofthe pulse, the output of said delay circuit providing modified pulses (JJ which are shortened with respect to the pulses (J) from the source bysaid predetermined time o);

two similar channels forming signal translation circuits, and achange-over switch (40), the changeover switch being connected toreceive the modified, shortened pulses (J J and a ply said modifiedpulses alternately to one and t e other signal translation channels;

each said channel including a condenser (11, 12),

means (L L charging the condenser during the connection of the modifiedpulse by said changeover switch to the respective channel to a levelrepresentative of the duration of said modified pulse,

and a discharge circuit (105, 107, 101; 114) for the condenser (ll, 12)partially discharging the respective condenser to a predeterminedremaining charge level (U means connecting the fully charged condenserof a respective one channel to said indicator means (10) to provide anindication of the length of a pulse;

and means controlled by termination of the subsequent pulse connectingthe discharge circuit to the condenser of said respective one channel todischarge the respective one condenser to said remaining charge leveland permit charging the respective one condenser in accordance with theduration of the second next modified pulse after said predetermined timewhile the fully charged condenser of the other channel is connected tothe indicator means to provide an indication of the next subsequentpulse.

13. Apparatus according to claim 12, wherein the delay circuit comprisesa differentiator (15) and a monostable multivibrator (20) connected inseries to the input pulse source;

and a pulse subtraction stage (30) providing no output upon conjointoccurrence of the input pulse and the pulse from the monostablemultivibrator to provide an output pulse therefrom which forms saidmodified pulse shortened by the unstable time of the monostablemultivibrator, said unstable time being said predetermined time (t 14.Apparatus according to claim 12, wherein the discharge circuit comprisesa control transistor (101), a source of voltage (25,

35), and a voltage divider network (105, 107) serially connecting theemitter-collector path of the control transistor (101) to the source;

and means (114) connecting the respective condenser to the tap point ofthe voltage divider in the emitter-collector path of the controltransistor under command of the termination of a signal from the pulsesource, to discharge the condenser to said remaining charge leveldetermined by the voltage division ratio of the voltage divider and theresistance of the emitter-collector path of the transistor. 15.Apparatus according to claim 12, wherein each said signal translationcircuit has two output transistors (T,, T T T both connected as emitterfollowers, the collectors of both the transistors, of each channel,being connected together and to said single indicator means (10), thetransistors of each channel being connected to the change-over switch(40) to be alternately rendered conductive thereby.

* it k =8

1. Pulse length measuring circuit arrangement to provide an electricalvoltage or current representative of duration of input pulses comprisingat least one charging condenser; a constant current source; meansconnecting the constant current source to charge the condenser duringoccurrence of the pulse; means sensing the charge on the condenser toprovide a measure of the duration of the input pulse; means dischargingthe condenser to a predetermined charge level representative of apredetermined time duration to provide a predetermined minimum charge onthe condenser; and delay means connected to delay, by said predeterminedtime, connection of the constant current source to the condenser by saidconnection means, to avoid charging the condenser from completelydischarged state.
 2. Circuit arrangement according to claim 1, tomeasure the time duration of individual pulses of a train of pulses,wherein a pair of condensers are charged in alternate sequence. 3.Circuit arrangement according to claim 2, including a bistable flip-flophaving a pair of oppositely poled outputs; AND-gates connected to saidcondensers, and means connecting the outputs to respective AND-gatesassociated with the condensers to selectively enable said AND-gates andthus application of pulses to one or the other condenser and to permitread-out of the charge from one or the other condenser.
 4. Circuitarrangement according to claim 3, wherein said sensing means includes apair of transistors one, each, being connected to a respectivecondenser, a measuring instrument, the output of the respectivetransistor being applied in parallel to the measuring instrument, saidtransistors being connected to the outputs of the bistable flip-flop andselectively enabled.
 5. Circuit arrangement according to claim 2,including a bistable flip-flop having a pair of oppositely poledoutputs, and further comprising a pair of input AND-gates, one each gatebeing connected to a respective charging circuit of a condenser; a pairof output AND-gates, one each output AND-gate being connected to arespective discharge circuit of the condenser; and means interconnectingthe outputs from the flip-flop and the charging circuit of one condenserwhile connecting the discharge circuit of the other, in alternatesequences, to permit reading of the charge on one condenser while theother is charging, and vice versa.
 6. Circuit arrangement according toclaim 1, wherein the sensing means comprises a transistor having itsbase connected to the condenser.
 7. Circuit arrangement according toclaim 6, wherein the transistor is connected as an emitter-follower. 8.Circuit arrangement according to claim 7, wherein the transistor is afield effect transistor.
 9. Circuit arrangement according to claim 6,wherein the transistor is connected in a Darlington circuit.
 10. Circuitarrangement according to claim 6, wherein the sensing means includes acurrent measuring instrument connected to the transistor.
 11. Circuitarrangement according to claim 1, wherein the condenser discharge meanscomprises a control transistor (101); a source of voltage (25, 35); avoltage divider network (105, 107) serially connecting theemitter-collector path to the source; and means (114) connecting thecondenser (11) to the tap point of the voltage divider in theemitter-collector path of the control transistor to discharge thecondenser to a level determined by the voltage division ratio of thevoltage divider and the resistance of the emitter-collector path of thetransistor.
 12. Pulse length measuring apparatus comprising a singleindicator means (10); a single pulse source (J); a delay circuit (15,20, 30) delaying start of the pulse by a predetermined time (to) butbeing ineffective to delay termination of the pulse, the output of saiddelay circuit providing modified pulses (J10, J20) which are shortenedwith respect to the pulses (J) from the source by said predeterminedtime (to); two similar channels forming signal translation circuits, anda change-over switch (40), the change-over switch being connected toreceive the modified, shortened pulses (J10, J20) and apply saidmodified pulses alternately to one and the other signal translationchannels; each said channel including a condenser (11, 12), means (L1,L2) charging the condenser during the connection of the modified pulseby said change-over switch to the respective channel to a levelrepresentative of the duration of said modified pulse, and a dischargecircuit (105, 107, 101; 114) for the condenser (11, 12) partiallydischarging the respective condenser to a predetermined remaining chargelevel (Uo); means connecting the fully charged condenser of a respectiveone channel to said indicator means (10) to provide an indication of thelength of a pulse; and means controlled by termination of the subsequentpulse connecting the discharge circuit to the condenser of saidrespective one channel to discharge the respective one condenser to saidremaining charge level and permit charging the respective one condenserin accordance with the duration of the second next modified pulse aftersaid predetermined time while the fully charged condenser of the otherchannel is connected to the indicator means to provide an indication ofthe next subsequent pulse.
 13. Apparatus according to claim 12, whereinthe delay circuit comprises a differentiator (15) and a monostablemultivibrator (20) connected in series to the input pulse source; and apulse subtraction stage (30) providing no output upon conjointoccurrence of the input pulse and the pulse from the monostablemultivibrator to provide an output pulse therefrom which forms saidmodified pulse shortened by the unstable time of the monostablemultivibrator, said unstable time being said predetermined time (t0).14. Apparatus according to claim 12, wherein the discharge circuitcomprises a control transistor (101), a source of voltage (25, 35), anda voltage divider network (105, 107) serially connecting theemitter-collector path of the control transistor (101) to the source;and means (114) connecting the respective condenser to the tap point ofthe voltage divider in the emitter-collector path of the controltransistor under command of the termination of a signal From the pulsesource, to discharge the condenser to said remaining charge leveldetermined by the voltage division ratio of the voltage divider and theresistance of the emitter-collector path of the transistor. 15.Apparatus according to claim 12, wherein each said signal translationcircuit has two output transistors (T1, T11; T2, T12), both connected asemitter followers, the collectors of both the transistors, of eachchannel, being connected together and to said single indicator means(10), the transistors of each channel being connected to the change-overswitch (40) to be alternately rendered conductive thereby.